The present disclosure is related to the following commonly-assigned patent applications, the entire disclosures of which are incorporated herein by reference: U.S. Provisional Patent Application Ser. No. 62/019,100 filed on Jun. 30, 2014, entitled “Mechanisms for Forming Patterns Using Multiple Lithography Processes”, and U.S. patent application Ser. No. 14/210,032 filed on Mar. 13, 2014, entitled “Mechanisms for Forming Patterns Using Multiple Lithography Processes”.
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In the course of these benefits, efforts have been made to develop fabrication methods to realize the desire for smaller feature sizes. For example, methods have been developed to reduce the pitch of features on a substrate without changing the photolithography technology used. However, current methods have not been satisfactory in all respects. For example, process windows of critical dimension (CD) uniformity control and process flexibility of forming special features may be not sufficient.